As the critical dimensions of integrated circuits continue to shrink, a common difficulty faced by both planar and non-planar transistor structures is source-to-drain leakage. Typically, halo or punchthrough implants are used as counterdoped regions under or proximate the channel region to minimize source-to-drain leakage. However, formation of such implants often causes undesirable doping of, or other damage to, the channel region. Further, these implants are frequently not sufficient to inhibit source-to-drain leakage.
A process for inhibiting source-to-drain leakage in planar transistor structures is the use of “silicon-on-nothing” or “SON” technology to form an insulator under the gate. Heretofore, such a process has not been effectively utilized for non-planar multigate field effect transistor devices, referred to herein generally as FinFETS. The planar SON process forms a void under the transistor channel material while anchoring the transistor channel material from above with the already-formed gate. However, for bulk FinFETs, the presence of the gate over the transistor channel material during SON process void formation causes several drawbacks including gate length dependence of the removal process.
Accordingly, it is desirable to provide methods for fabricating integrated circuits with FinFET devices having reduced source-to-drain leakage. Further, it is desirable to provide methods for fabricating bulk FinFET transistors having channel regions isolated from the substrate. It is also desirable to provide methods for fabricating bulk FinFET transistors that form voids under active channel regions using gate length independent etching processes. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.